Integrated circuits are operated in environments where radiation-induced logic errors may occur, such as in outer space. In such environments, the integrated circuit is required to maintain data integrity during a single-event upset (SEU). A single-event upset is a radiation-induced error in the logic state of a signal within the integrated circuit. Such a single-event upset may be the result of a collision between a high-energy proton or a heavy ion (cosmic ray) and the semiconductor material that forms the integrated circuit. The interaction of these charged particles, or heavy ions, with metal oxide semiconductor (MOS) static random access memory (SRAM) cells results in low linear energy transfer (LET) from the charged particle to the SRAM cells.
The basic operation of the SRAM cell is to store electronic information in the form of 1's and 0's. In space-based electronics, where cosmic-rays exist and bombard electronics continuously, LET from a heavy ion's interaction with an SRAM cell can flip/change the state of that cell's stored information from a 0 to a 1 (or a 1 to a 0). This interaction corrupts stored information and can lead to incorrect operation of associated circuitry. To prevent single-event upsets from causing erroneous operation of an integrated circuit containing SRAM cells, circuitry within the integrated circuit must be designed to withstand such upsets.
A simple six-transistor SRAM cell is shown in FIG. 1. A bit in the SRAM cell 100 is stored through four transistors 110-113 that together form two cross-coupled inverters 101 and 102 disposed between reference voltages VDD and GND. Inverter 101 comprises P-type field-effect-transistor (“P-fet”) 110 and N-type field-effect-transistor (“N-fet”) 111 while inverter 102 comprises P-fet 112 and N-fet 113. The control gates of transistors 110 and 111 are commonly connected at first output node Q and the control gates of transistors 112 and 113 are commonly connected at second output node Qbar. The storage cell 100 has two stable states which are respectively used to denote a logical 0 and a logical 1.
Two additional access transistors 103 and 104 serve to control the access to data stored on the output nodes Q, Qbar during read and write operations. Upon charging of a word line WL coupled to the gates of these access transistors 103 and 104, the access transistors turn ON and transfer data stored on the output nodes Q, Qbar onto the bitlines BLT and BLC.
In operation, to access data stored in the SRAM cell 100 the wordline WL is activated to turn ON the access transistors 103 and 104. The cell 100 thereafter transfers the data stored in the cell in the form of the voltages on the output nodes Q, Qbar onto the bitlines BLT, BLC during a read operation. During a write operation, voltages are applied on the bitlines BLT, BLC corresponding to the data to the stored in the cell 100 to thereby drive the voltages on the nodes Q, Qbar to the desired voltages. In the SRAM cell 100, even when turned OFF the transistor may be in saturation with Vdd applied across its source and drain, which increases the LET-sensitivity of the memory cell, and concomitantly increases the likelihood of a single-event upset causing an error flipping the state of the cell, as described in further detail with respect to FIGS. 2A-2C below.
To examine the scenario resulting from an SEU impact of SRAM memory cell 100, assume that the bit stored in cell 100 is a logical 1, meaning output node Q is at approximately Vdd and output node Qbar at approximately ground. N-fet 113 and P-fet 110 are consequently both off, while N-fet 111 is ON and “pulling down” node Qbar just as P-fet 112 is “pulling up” output node Q. Although N-fet 113 is off, it is in saturation mode due to the voltage across its drain coupled to node Q and its source connected to ground. Similarly, P-fet 110 is off but also in saturation mode since a voltage of approximately Vdd is across its source and drain.
FIG. 2A shows a cross-section of N-type transistor 113 from FIG. 1 while off but in saturation mode, such as when memory cell 100 stores a logical 1. Transistor 113 is disposed in a substrate 201. Source 210 is connected to GND. Gate 220 is tied to Qbar, which is also in its low-voltage state (equivalent to GND) because memory cell 100 is storing a logical 1. Similarly, drain 230 is connected to Vdd by Q being in its high-voltage state. FIG. 2A also shows a single-event upset in the form of an impact from heavy ion 299, which results in additional charge via linear energy transfer (LET) in the area of substrate 210 between source 210 and drain 230. FIG. 2B shows this additional ion-charge deposition allowing a conduction channel 240 to form between source 210 and drain 230. This interaction turns transistor 1130N, driving node Q to a low-voltage state which, in turn, drives node Qbar high thus changes or flips the state of the memory cell 100. This causes a “soft error” of the data stored in the memory cell 100. A soft error is one which results the change of data stored in an SRAM memory cell but which does not damage the circuitry of the cell.
FIG. 3 shows an SEU-resistant improvement to the design of the basic six-transistor SRAM memory cell 100 discussed above with respect to FIG. 1A. Cross-coupled resistors 310 and 320, often called feedback resistors, are respectively connected between output nodes Q and Qbar and the control nodes of inverters 101 and 102. This resistance operates to decrease the LET-sensitivity of memory cell 300. However, as silicon technology has scaled in line-width dimension into the deep sub-micron range (0.25 μm and smaller) process control in the manufacturing of these feedback resistors has increased in difficulty.
FIG. 4 shows a known improved SRAM memory cell with a 10-transistor (10-T) configuration. This cell design uses secondary transistors, identified as P-fet (ohm) 450 and P-fet (ohm) 452 and N-fet (ohm) 451 and N-fet (ohm) 453 to provide ohmic channel resistance. P-fet 450 is inserted between pull-up P-fet 110 and output node Qbar; P-fet 452 is inserted between pull-up P-fet 112 and output node Q. Both P-fets 450 and 452 are gate-tied to GND such that they are powered in a permanent ON-state. Similarly, N-fet 451 is inserted between pull-down N-fet 111 and output node Qbar; N-fet 453 is inserted between pull-down N-fet 113 and output node Q. Both N-fets 451 and 453 are gate-tied to Vdd such that they, too, are powered in a permanent ON-state. The inline resistance of this configuration allows transistors 450-453 to operate as a voltage divider element to provide feedback resistance in the cell, much like resistors 310 and 320 operate with respect to memory cell 300 in FIG. 3. While improved, the design has a high LET sensitivity: the cell will upset with a heavy-ion LET as low as 9 (MeV cm2)/mg. The desired LET sensitivity would be above 40 (MeV cm2)/mg.